The present invention relates to a storage control apparatus and, more particularly, to a storage control apparatus adapted to access a main storage unit in response to access requests from input-output processor, an instruction processor and the like.
In a multiple processing system adapted to share a main storage unit with various processors by making plural input-output processors and plural instruction processors, access to the main storage unit through a storage control apparatus in which a cache memory is provided. Access control over the main storage unit can be carried out by processing a memory access request from each of the input-output processors and the instruction processors.
Heretofore, the access control over the main storage unit of this kind is known to be of the type of a buffer storage control as disclosed, for example, in Japanese Patent Publication (laid-open) No. 154,039/1987. The buffer storage control type is a storage control type in which the buffer storage (cache memory) is shared with plural central processing units, and the buffer storage is read or written in a store-in system. In this type, there disposed a register holding a block address which is memory replaces in buffer storage for the access requests from the plural central processing units, and an access to the block address held in the register is prohibited until a memory block transfer containing a desired data for an access request to the buffer storage from the main storage and an address registration of an address array is finished. As this does not affect processing for invalidating the address array corresponding to the replace block if the memory data required does not exist in the buffer storage, the address array can be retrieved without awaiting a memory access which follows. Thus improving a throughput of the address array, that is, a throughput of the buffer storage.
It is, however, to be noted that, in the buffer storage control type, when the memory data required is not stored in the buffer storage, the buffer storage can be made accessible without the following access request from a device as a source of issuing a different access request being waited, thus improving a throughput of the memory access.
However, nothing is taken into consideration about the case that a memory access request which follows is issued from the same device as in the previous memory access request. Accordingly, if the following memory access request is issued from the same device as the previous memory access request, the following memory access request remains waiting. In other words, if plural requests are issued one after another from the same device, the following request is awaited during a period of time when the previous request awaits a data transfer from the main storage; although it can access a cache memory. For this reason, when plural requests are issued one after another from the same device, the following request is awaited for a longer time, thus reducing a total throughput.